An Efficient Vlsi Implementation for the Soft Information-set Decoding Algorithm
نویسندگان
چکیده
Error-correcting codes are present in basically all modern data communications and data storage systems. When top-performance is required, the corresponding algorithms (encoder + decoder) are implemented in hardware. This paper describes a VLSI implementation for an information-set-based error correcting decoder. More specifically, we present the modified Gauss-Jordan elimination block, which constitutes the main block of the ongoing work on the complete soft information-set decoder. The motivation for this work is that such decoder can achieve near-MLD performance with fewer computations, but no VLSI implementation has been developed for it yet.
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